50 lines
1.8 KiB
C
50 lines
1.8 KiB
C
#include "../io.h"
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#define PIC1 0x20 /* IO base address for master PIC */
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#define PIC2 0xA0 /* IO base address for slave PIC */
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#define PIC1_COMMAND PIC1
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#define PIC1_DATA (PIC1+1)
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2+1)
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#define ICW1_ICW4 0x01 /* Indicates that ICW4 will be present */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization - required! */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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void init_pic() {
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uint8_t a1;
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a1 = inb(PIC1_DATA); // save masks
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inb(PIC2_DATA);
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outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the initialization sequence (in cascade mode)
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io_wait();
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outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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outb(PIC1_DATA, 0x20); // ICW2: Master PIC vector offset
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io_wait();
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outb(PIC2_DATA, 0xFF); // ICW2: Slave PIC vector offset
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io_wait();
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outb(PIC1_DATA, 4); // ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
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io_wait();
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outb(PIC2_DATA, 2); // ICW3: tell Slave PIC its cascade identity (0000 0010)
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io_wait();
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outb(PIC1_DATA, ICW4_8086); // ICW4: have the PICs use 8086 mode (and not 8080 mode)
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io_wait();
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outb(PIC2_DATA, ICW4_8086);
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io_wait();
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outb(PIC1_DATA, a1); // restore saved masks.
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// outb(PIC2_DATA, a2);
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outb(PIC2_DATA, 0xFF);
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}
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