529 lines
18 KiB
C++
529 lines
18 KiB
C++
/* Local Register Allocator (LRA) intercommunication header file.
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Copyright (C) 2010-2023 Free Software Foundation, Inc.
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Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_LRA_INT_H
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#define GCC_LRA_INT_H
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#define lra_assert(c) gcc_checking_assert (c)
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/* The parameter used to prevent infinite reloading for an insn. Each
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insn operands might require a reload and, if it is a memory, its
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base and index registers might require a reload too. */
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#define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3)
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typedef struct lra_live_range *lra_live_range_t;
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/* The structure describes program points where a given pseudo lives.
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The live ranges can be used to find conflicts with other pseudos.
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If the live ranges of two pseudos are intersected, the pseudos are
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in conflict. */
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struct lra_live_range
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{
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/* Pseudo regno whose live range is described by given
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structure. */
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int regno;
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/* Program point range. */
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int start, finish;
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/* Next structure describing program points where the pseudo
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lives. */
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lra_live_range_t next;
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/* Pointer to structures with the same start. */
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lra_live_range_t start_next;
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};
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typedef struct lra_copy *lra_copy_t;
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/* Copy between pseudos which affects assigning hard registers. */
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struct lra_copy
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{
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/* True if regno1 is the destination of the copy. */
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bool regno1_dest_p;
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/* Execution frequency of the copy. */
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int freq;
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/* Pseudos connected by the copy. REGNO1 < REGNO2. */
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int regno1, regno2;
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/* Next copy with correspondingly REGNO1 and REGNO2. */
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lra_copy_t regno1_next, regno2_next;
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};
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/* Common info about a register (pseudo or hard register). */
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class lra_reg
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{
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public:
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/* Bitmap of UIDs of insns (including debug insns) referring the
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reg. */
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bitmap_head insn_bitmap;
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/* The following fields are defined only for pseudos. */
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/* Hard registers with which the pseudo conflicts. */
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HARD_REG_SET conflict_hard_regs;
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/* Pseudo allocno class hard registers which cannot be a start hard register
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of the pseudo. */
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HARD_REG_SET exclude_start_hard_regs;
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/* We assign hard registers to reload pseudos which can occur in few
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places. So two hard register preferences are enough for them.
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The following fields define the preferred hard registers. If
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there are no such hard registers the first field value is
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negative. If there is only one preferred hard register, the 2nd
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field is negative. */
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int preferred_hard_regno1, preferred_hard_regno2;
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/* Profits to use the corresponding preferred hard registers. If
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the both hard registers defined, the first hard register has not
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less profit than the second one. */
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int preferred_hard_regno_profit1, preferred_hard_regno_profit2;
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#ifdef STACK_REGS
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/* True if the pseudo should not be assigned to a stack register. */
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bool no_stack_p;
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#endif
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/* Number of references and execution frequencies of the register in
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*non-debug* insns. */
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int nrefs, freq;
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int last_reload;
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/* rtx used to undo the inheritance. It can be non-null only
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between subsequent inheritance and undo inheritance passes. */
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rtx restore_rtx;
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/* Value holding by register. If the pseudos have the same value
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they do not conflict. */
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int val;
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/* Offset from relative eliminate register to pesudo reg. */
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poly_int64 offset;
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/* These members are set up in lra-lives.cc and updated in
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lra-coalesce.cc. */
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/* The biggest size mode in which each pseudo reg is referred in
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whole function (possibly via subreg). */
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machine_mode biggest_mode;
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/* Live ranges of the pseudo. */
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lra_live_range_t live_ranges;
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/* This member is set up in lra-lives.cc for subsequent
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assignments. */
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lra_copy_t copies;
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};
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/* References to the common info about each register. */
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extern class lra_reg *lra_reg_info;
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extern HARD_REG_SET hard_regs_spilled_into;
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/* Static info about each insn operand (common for all insns with the
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same ICODE). Warning: if the structure definition is changed, the
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initializer for debug_operand_data in lra.cc should be changed
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too. */
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struct lra_operand_data
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{
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/* The machine description constraint string of the operand. */
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const char *constraint;
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/* Alternatives for which early_clobber can be true. */
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alternative_mask early_clobber_alts;
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/* It is taken only from machine description (which is different
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from recog_data.operand_mode) and can be of VOIDmode. */
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ENUM_BITFIELD(machine_mode) mode : 16;
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/* The type of the operand (in/out/inout). */
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ENUM_BITFIELD (op_type) type : 8;
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/* Through if accessed through STRICT_LOW. */
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unsigned int strict_low : 1;
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/* True if the operand is an operator. */
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unsigned int is_operator : 1;
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/* True if the operand is an address. */
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unsigned int is_address : 1;
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};
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/* Info about register occurrence in an insn. */
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struct lra_insn_reg
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{
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/* Alternatives for which early_clobber can be true. */
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alternative_mask early_clobber_alts;
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/* The biggest mode through which the insn refers to the register
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occurrence (remember the register can be accessed through a
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subreg in the insn). */
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ENUM_BITFIELD(machine_mode) biggest_mode : 16;
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/* The type of the corresponding operand which is the register. */
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ENUM_BITFIELD (op_type) type : 8;
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/* True if the reg is accessed through a subreg and the subreg is
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just a part of the register. */
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unsigned int subreg_p : 1;
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/* The corresponding regno of the register. */
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int regno;
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/* Next reg info of the same insn. */
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struct lra_insn_reg *next;
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};
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/* Static part (common info for insns with the same ICODE) of LRA
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internal insn info. It exists in at most one exemplar for each
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non-negative ICODE. There is only one exception. Each asm insn has
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own structure. Warning: if the structure definition is changed,
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the initializer for debug_insn_static_data in lra.cc should be
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changed too. */
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struct lra_static_insn_data
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{
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/* Static info about each insn operand. */
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struct lra_operand_data *operand;
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/* Each duplication refers to the number of the corresponding
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operand which is duplicated. */
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int *dup_num;
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/* The number of an operand marked as commutative, -1 otherwise. */
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int commutative;
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/* Number of operands, duplications, and alternatives of the
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insn. */
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char n_operands;
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char n_dups;
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char n_alternatives;
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/* Insns in machine description (or clobbers in asm) may contain
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explicit hard regs which are not operands. The following list
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describes such hard registers. */
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struct lra_insn_reg *hard_regs;
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/* Array [n_alternatives][n_operand] of static constraint info for
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given operand in given alternative. This info can be changed if
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the target reg info is changed. */
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const struct operand_alternative *operand_alternative;
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};
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/* Negative insn alternative numbers used for special cases. */
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#define LRA_UNKNOWN_ALT -1
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#define LRA_NON_CLOBBERED_ALT -2
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/* LRA internal info about an insn (LRA internal insn
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representation). */
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class lra_insn_recog_data
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{
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public:
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/* The insn code. */
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int icode;
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/* The alternative should be used for the insn, LRA_UNKNOWN_ALT if
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unknown, or we should assume any alternative, or the insn is a
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debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier
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clobbers for the insn. */
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int used_insn_alternative;
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/* SP offset before the insn relative to one at the func start. */
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poly_int64 sp_offset;
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/* The insn itself. */
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rtx_insn *insn;
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/* Common data for insns with the same ICODE. Asm insns (their
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ICODE is negative) do not share such structures. */
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struct lra_static_insn_data *insn_static_data;
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/* Two arrays of size correspondingly equal to the operand and the
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duplication numbers: */
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rtx **operand_loc; /* The operand locations, NULL if no operands. */
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rtx **dup_loc; /* The dup locations, NULL if no dups. */
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/* Number of hard registers implicitly used/clobbered in given call
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insn. The value can be NULL or points to array of the hard
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register numbers ending with a negative value. To differ
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clobbered and used hard regs, clobbered hard regs are incremented
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by FIRST_PSEUDO_REGISTER. */
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int *arg_hard_regs;
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/* Cached value of get_preferred_alternatives. */
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alternative_mask preferred_alternatives;
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/* The following member value is always NULL for a debug insn. */
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struct lra_insn_reg *regs;
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};
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typedef class lra_insn_recog_data *lra_insn_recog_data_t;
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/* Whether the clobber is used temporary in LRA. */
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#define LRA_TEMP_CLOBBER_P(x) \
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(RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging)
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/* Cost factor for each additional reload and maximal cost reject for
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insn reloads. One might ask about such strange numbers. Their
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values occurred historically from former reload pass. */
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#define LRA_LOSER_COST_FACTOR 6
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#define LRA_MAX_REJECT 600
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/* Maximum allowed number of assignment pass iterations after the
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latest spill pass when any former reload pseudo was spilled. It is
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for preventing LRA cycling in a bug case. */
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#define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30
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/* The maximal number of inheritance/split passes in LRA. It should
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be more 1 in order to perform caller saves transformations and much
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less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many
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as permitted constraint passes in some complicated cases. The
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first inheritance/split pass has a biggest impact on generated code
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quality. Each subsequent affects generated code in less degree.
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For example, the 3rd pass does not change generated SPEC2000 code
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at all on x86-64. */
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#define LRA_MAX_INHERITANCE_PASSES 2
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#if LRA_MAX_INHERITANCE_PASSES <= 0 \
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|| LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
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#error wrong LRA_MAX_INHERITANCE_PASSES value
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#endif
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/* Analogous macro to the above one but for rematerialization. */
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#define LRA_MAX_REMATERIALIZATION_PASSES 2
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#if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \
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|| LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
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#error wrong LRA_MAX_REMATERIALIZATION_PASSES value
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#endif
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/* lra.cc: */
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extern FILE *lra_dump_file;
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extern bool lra_hard_reg_split_p;
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extern bool lra_asm_error_p;
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extern bool lra_reg_spill_p;
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extern HARD_REG_SET lra_no_alloc_regs;
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extern int lra_insn_recog_data_len;
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extern lra_insn_recog_data_t *lra_insn_recog_data;
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extern int lra_curr_reload_num;
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extern void lra_dump_bitmap_with_title (const char *, bitmap, int);
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extern hashval_t lra_rtx_hash (rtx x);
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extern void lra_push_insn (rtx_insn *);
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extern void lra_push_insn_by_uid (unsigned int);
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extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *);
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extern rtx_insn *lra_pop_insn (void);
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extern unsigned int lra_insn_stack_length (void);
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extern rtx lra_create_new_reg (machine_mode, rtx, enum reg_class, HARD_REG_SET *,
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const char *);
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extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx,
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enum reg_class, HARD_REG_SET *,
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const char *);
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extern void lra_set_regno_unique_value (int);
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extern void lra_invalidate_insn_data (rtx_insn *);
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extern void lra_set_insn_deleted (rtx_insn *);
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extern void lra_delete_dead_insn (rtx_insn *);
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extern void lra_emit_add (rtx, rtx, rtx);
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extern void lra_emit_move (rtx, rtx);
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extern void lra_update_dups (lra_insn_recog_data_t, signed char *);
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extern void lra_process_new_insns (rtx_insn *, rtx_insn *, rtx_insn *,
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const char *);
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extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool);
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extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool);
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extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *);
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extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *);
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extern void lra_set_used_insn_alternative (rtx_insn *, int);
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extern void lra_set_used_insn_alternative_by_uid (int, int);
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extern void lra_invalidate_insn_regno_info (rtx_insn *);
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extern void lra_update_insn_regno_info (rtx_insn *);
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extern struct lra_insn_reg *lra_get_insn_regs (int);
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extern void lra_free_copies (void);
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extern void lra_create_copy (int, int, int);
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extern lra_copy_t lra_get_copy (int);
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extern int lra_new_regno_start;
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extern int lra_constraint_new_regno_start;
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extern int lra_bad_spill_regno_start;
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extern rtx lra_pmode_pseudo;
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extern bitmap_head lra_inheritance_pseudos;
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extern bitmap_head lra_split_regs;
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extern bitmap_head lra_subreg_reload_pseudos;
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extern bitmap_head lra_optional_reload_pseudos;
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/* lra-constraints.cc: */
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extern void lra_init_equiv (void);
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extern int lra_constraint_offset (int, machine_mode);
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extern int lra_constraint_iter;
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extern bool check_and_force_assignment_correctness_p;
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extern int lra_inheritance_iter;
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extern int lra_undo_inheritance_iter;
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extern bool lra_constrain_insn (rtx_insn *);
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extern bool lra_constraints (bool);
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extern void lra_constraints_init (void);
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extern void lra_constraints_finish (void);
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extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *);
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extern void lra_inheritance (void);
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extern bool lra_undo_inheritance (void);
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/* lra-lives.cc: */
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extern int lra_live_max_point;
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extern int *lra_point_freq;
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extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER];
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extern int lra_live_range_iter;
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extern void lra_create_live_ranges (bool, bool);
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extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t);
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extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t,
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lra_live_range_t);
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extern bool lra_intersected_live_ranges_p (lra_live_range_t,
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lra_live_range_t);
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extern void lra_print_live_range_list (FILE *, lra_live_range_t);
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extern void debug (lra_live_range &ref);
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extern void debug (lra_live_range *ptr);
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extern void lra_debug_live_range_list (lra_live_range_t);
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extern void lra_debug_pseudo_live_ranges (int);
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extern void lra_debug_live_ranges (void);
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extern void lra_clear_live_ranges (void);
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extern void lra_live_ranges_init (void);
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extern void lra_live_ranges_finish (void);
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extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int);
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/* lra-assigns.cc: */
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extern int lra_assignment_iter;
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extern int lra_assignment_iter_after_spill;
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extern void lra_setup_reg_renumber (int, int, bool);
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extern bool lra_assign (bool &);
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extern bool lra_split_hard_reg_for (void);
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/* lra-coalesce.cc: */
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extern int lra_coalesce_iter;
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extern bool lra_coalesce (void);
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/* lra-spills.cc: */
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extern bool lra_need_for_scratch_reg_p (void);
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extern bool lra_need_for_spills_p (void);
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extern void lra_spill (void);
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extern void lra_final_code_change (void);
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/* lra-remat.cc: */
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extern int lra_rematerialization_iter;
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extern bool lra_remat (void);
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/* lra-elimination.c: */
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extern void lra_debug_elim_table (void);
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extern int lra_get_elimination_hard_regno (int);
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extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode,
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bool, bool, poly_int64, bool);
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extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64);
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extern void lra_eliminate (bool, bool);
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extern void lra_eliminate_reg_if_possible (rtx *);
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/* Return the hard register which given pseudo REGNO assigned to.
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Negative value means that the register got memory or we don't know
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allocation yet. */
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inline int
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lra_get_regno_hard_regno (int regno)
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{
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resize_reg_info ();
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return reg_renumber[regno];
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}
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/* Change class of pseudo REGNO to NEW_CLASS. Print info about it
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using TITLE. Output a new line if NL_P. */
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inline void
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lra_change_class (int regno, enum reg_class new_class,
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const char *title, bool nl_p)
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{
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lra_assert (regno >= FIRST_PSEUDO_REGISTER);
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if (lra_dump_file != NULL)
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fprintf (lra_dump_file, "%s class %s for r%d",
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title, reg_class_names[new_class], regno);
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setup_reg_classes (regno, new_class, NO_REGS, new_class);
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if (lra_dump_file != NULL && nl_p)
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fprintf (lra_dump_file, "\n");
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}
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/* Update insn operands which are duplication of NOP operand. The
|
||
insn is represented by its LRA internal representation ID. */
|
||
inline void
|
||
lra_update_dup (lra_insn_recog_data_t id, int nop)
|
||
{
|
||
int i;
|
||
struct lra_static_insn_data *static_id = id->insn_static_data;
|
||
|
||
for (i = 0; i < static_id->n_dups; i++)
|
||
if (static_id->dup_num[i] == nop)
|
||
*id->dup_loc[i] = *id->operand_loc[nop];
|
||
}
|
||
|
||
/* Process operator duplications in insn with ID. We do it after the
|
||
operands processing. Generally speaking, we could do this probably
|
||
simultaneously with operands processing because a common practice
|
||
is to enumerate the operators after their operands. */
|
||
inline void
|
||
lra_update_operator_dups (lra_insn_recog_data_t id)
|
||
{
|
||
int i;
|
||
struct lra_static_insn_data *static_id = id->insn_static_data;
|
||
|
||
for (i = 0; i < static_id->n_dups; i++)
|
||
{
|
||
int ndup = static_id->dup_num[i];
|
||
|
||
if (static_id->operand[ndup].is_operator)
|
||
*id->dup_loc[i] = *id->operand_loc[ndup];
|
||
}
|
||
}
|
||
|
||
/* Return info about INSN. Set up the info if it is not done yet. */
|
||
inline lra_insn_recog_data_t
|
||
lra_get_insn_recog_data (rtx_insn *insn)
|
||
{
|
||
lra_insn_recog_data_t data;
|
||
unsigned int uid = INSN_UID (insn);
|
||
|
||
if (lra_insn_recog_data_len > (int) uid
|
||
&& (data = lra_insn_recog_data[uid]) != NULL)
|
||
{
|
||
/* Check that we did not change insn without updating the insn
|
||
info. */
|
||
lra_assert (data->insn == insn
|
||
&& (INSN_CODE (insn) < 0
|
||
|| data->icode == INSN_CODE (insn)));
|
||
return data;
|
||
}
|
||
return lra_set_insn_recog_data (insn);
|
||
}
|
||
|
||
/* Update offset from pseudos with VAL by INCR. */
|
||
inline void
|
||
lra_update_reg_val_offset (int val, poly_int64 incr)
|
||
{
|
||
int i;
|
||
|
||
for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
|
||
{
|
||
if (lra_reg_info[i].val == val)
|
||
lra_reg_info[i].offset += incr;
|
||
}
|
||
}
|
||
|
||
/* Return true if register content is equal to VAL with OFFSET. */
|
||
inline bool
|
||
lra_reg_val_equal_p (int regno, int val, poly_int64 offset)
|
||
{
|
||
if (lra_reg_info[regno].val == val
|
||
&& known_eq (lra_reg_info[regno].offset, offset))
|
||
return true;
|
||
|
||
return false;
|
||
}
|
||
|
||
/* Assign value of register FROM to TO. */
|
||
inline void
|
||
lra_assign_reg_val (int from, int to)
|
||
{
|
||
lra_reg_info[to].val = lra_reg_info[from].val;
|
||
lra_reg_info[to].offset = lra_reg_info[from].offset;
|
||
}
|
||
|
||
#endif /* GCC_LRA_INT_H */
|