246 lines
9.7 KiB
C
246 lines
9.7 KiB
C
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/* Communication between the Integrated Register Allocator (IRA) and
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the rest of the compiler.
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Copyright (C) 2006-2023 Free Software Foundation, Inc.
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Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_IRA_H
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#define GCC_IRA_H
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#include "emit-rtl.h"
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/* True when we use LRA instead of reload pass for the current
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function. */
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extern bool ira_use_lra_p;
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/* True if we have allocno conflicts. It is false for non-optimized
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mode or when the conflict table is too big. */
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extern bool ira_conflicts_p;
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struct target_ira
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{
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/* Map: hard register number -> allocno class it belongs to. If the
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corresponding class is NO_REGS, the hard register is not available
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for allocation. */
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enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
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/* Number of allocno classes. Allocno classes are register classes
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which can be used for allocations of allocnos. */
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int x_ira_allocno_classes_num;
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/* The array containing allocno classes. Only first
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IRA_ALLOCNO_CLASSES_NUM elements are used for this. */
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enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
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/* Map of all register classes to corresponding allocno classes
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containing the given class. If given class is not a subset of an
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allocno class, we translate it into the cheapest allocno class. */
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enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
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/* Number of pressure classes. Pressure classes are register
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classes for which we calculate register pressure. */
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int x_ira_pressure_classes_num;
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/* The array containing pressure classes. Only first
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IRA_PRESSURE_CLASSES_NUM elements are used for this. */
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enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
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/* Map of all register classes to corresponding pressure classes
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containing the given class. If given class is not a subset of an
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pressure class, we translate it into the cheapest pressure
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class. */
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enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
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/* Biggest pressure register class containing stack registers.
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NO_REGS if there are no stack registers. */
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enum reg_class x_ira_stack_reg_pressure_class;
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/* Maps: register class x machine mode -> maximal/minimal number of
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hard registers of given class needed to store value of given
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mode. */
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unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
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unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
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/* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */
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short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
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/* Array of number of hard registers of given class which are
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available for the allocation. The order is defined by the
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allocation order. */
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short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
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/* The number of elements of the above array for given register
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class. */
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int x_ira_class_hard_regs_num[N_REG_CLASSES];
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/* Register class subset relation: TRUE if the first class is a subset
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of the second one considering only hard registers available for the
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allocation. */
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int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
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/* The biggest class inside of intersection of the two classes (that
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is calculated taking only hard registers available for allocation
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into account. If the both classes contain no hard registers
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available for allocation, the value is calculated with taking all
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hard-registers including fixed ones into account. */
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enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
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/* True if the two classes (that is calculated taking only hard
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registers available for allocation into account; are
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intersected. */
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bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
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/* If class CL has a single allocatable register of mode M,
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index [CL][M] gives the number of that register, otherwise it is -1. */
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short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
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/* Function specific hard registers cannot be used for the register
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allocation. */
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HARD_REG_SET x_ira_no_alloc_regs;
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/* Array whose values are hard regset of hard registers available for
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the allocation of given register class whose targetm.hard_regno_mode_ok
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values for given mode are false. */
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HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
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/* When an allocatable hard register in given mode can not be placed in given
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register class, it is in the set of the following array element. It can
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happen only when given mode requires more one hard register. */
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HARD_REG_SET x_ira_exclude_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
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};
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extern struct target_ira default_target_ira;
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#if SWITCHABLE_TARGET
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extern struct target_ira *this_target_ira;
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#else
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#define this_target_ira (&default_target_ira)
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#endif
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#define ira_hard_regno_allocno_class \
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(this_target_ira->x_ira_hard_regno_allocno_class)
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#define ira_allocno_classes_num \
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(this_target_ira->x_ira_allocno_classes_num)
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#define ira_allocno_classes \
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(this_target_ira->x_ira_allocno_classes)
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#define ira_allocno_class_translate \
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(this_target_ira->x_ira_allocno_class_translate)
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#define ira_pressure_classes_num \
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(this_target_ira->x_ira_pressure_classes_num)
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#define ira_pressure_classes \
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(this_target_ira->x_ira_pressure_classes)
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#define ira_pressure_class_translate \
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(this_target_ira->x_ira_pressure_class_translate)
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#define ira_stack_reg_pressure_class \
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(this_target_ira->x_ira_stack_reg_pressure_class)
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#define ira_reg_class_max_nregs \
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(this_target_ira->x_ira_reg_class_max_nregs)
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#define ira_reg_class_min_nregs \
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(this_target_ira->x_ira_reg_class_min_nregs)
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#define ira_memory_move_cost \
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(this_target_ira->x_ira_memory_move_cost)
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#define ira_class_hard_regs \
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(this_target_ira->x_ira_class_hard_regs)
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#define ira_class_hard_regs_num \
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(this_target_ira->x_ira_class_hard_regs_num)
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#define ira_class_subset_p \
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(this_target_ira->x_ira_class_subset_p)
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#define ira_reg_class_subset \
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(this_target_ira->x_ira_reg_class_subset)
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#define ira_reg_classes_intersect_p \
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(this_target_ira->x_ira_reg_classes_intersect_p)
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#define ira_class_singleton \
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(this_target_ira->x_ira_class_singleton)
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#define ira_no_alloc_regs \
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(this_target_ira->x_ira_no_alloc_regs)
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#define ira_prohibited_class_mode_regs \
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(this_target_ira->x_ira_prohibited_class_mode_regs)
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#define ira_exclude_class_mode_regs \
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(this_target_ira->x_ira_exclude_class_mode_regs)
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/* Major structure describing equivalence info for a pseudo. */
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struct ira_reg_equiv_s
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{
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/* True if we can use this as a general equivalence. */
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bool defined_p;
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/* True if we can use this equivalence only for caller save/restore
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location. */
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bool caller_save_p;
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/* True if the usage of the equivalence is profitable. */
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bool profitable_p;
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/* Equiv. memory, constant, invariant, and initializing insns of
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given pseudo-register or NULL_RTX. */
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rtx memory;
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rtx constant;
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rtx invariant;
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/* Always NULL_RTX if defined_p is false. */
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rtx_insn_list *init_insns;
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};
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/* The length of the following array. */
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extern int ira_reg_equiv_len;
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/* Info about equiv. info for each register. */
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extern struct ira_reg_equiv_s *ira_reg_equiv;
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extern void ira_init_once (void);
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extern void ira_init (void);
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extern void ira_setup_eliminable_regset (void);
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extern rtx ira_eliminate_regs (rtx, machine_mode);
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extern void ira_set_pseudo_classes (bool, FILE *);
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extern void ira_expand_reg_equiv (void);
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extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
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extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *);
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extern void ira_mark_allocation_change (int);
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extern void ira_mark_memory_move_deletion (int, int);
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extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
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HARD_REG_SET *, bitmap);
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extern rtx ira_reuse_stack_slot (int, poly_uint64, poly_uint64);
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extern void ira_mark_new_stack_slot (rtx, int, poly_uint64);
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extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx_insn *);
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extern bool ira_bad_reload_regno (int, rtx, rtx);
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extern void ira_adjust_equiv_reg_cost (unsigned, int);
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extern bool ira_former_scratch_p (int regno);
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extern bool ira_former_scratch_operand_p (rtx_insn *insn, int nop);
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extern void ira_register_new_scratch_op (rtx_insn *insn, int nop, int icode);
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extern bool ira_remove_insn_scratches (rtx_insn *insn, bool all_p, FILE *dump_file,
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rtx (*get_reg) (rtx original));
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extern void ira_restore_scratches (FILE *dump_file);
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extern void ira_nullify_asm_goto (rtx_insn *insn);
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/* ira-costs.cc */
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extern void ira_costs_cc_finalize (void);
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/* ira-lives.cc */
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extern rtx non_conflicting_reg_copy_p (rtx_insn *);
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/* Spilling static chain pseudo may result in generation of wrong
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non-local goto code using frame-pointer to address saved stack
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pointer value after restoring old frame pointer value. The
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function returns TRUE if REGNO is such a static chain pseudo. */
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inline bool
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non_spilled_static_chain_regno_p (int regno)
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{
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return (cfun->static_chain_decl && crtl->has_nonlocal_goto
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&& REG_EXPR (regno_reg_rtx[regno]) == cfun->static_chain_decl);
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}
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#endif /* GCC_IRA_H */
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